The present invention relates generally to the field of computer circuit testing, and more particularly to a circuit for on-line AC and DC fault testing a clock distribution network
A standard power-up, fanout tree chip is generally used to distribute clock signals received from an external chip to various locations in a computer. The computer is highly sensitive to the performance of the clock distribution circuits of such a chip, because the addition of unanticipated AC delay during propagation through these circuits will typically result in arrays/latches being clocked late, and the occurrence of DC stuck faults will prevent memory operation.
In particular, experience has shown that significant numbers of small AC defects of less than 5 ns occur in clock distribution chips. Because these clock distribution chips feed more than one field replaceable unit (FRU) at a time, a small AC timing defect will generate errors in more than one Field Replaceable Unit (FRU) computer module at a time. A field engineer attempting to repair such a defect in a computer would thus be required to replace a number of FRU's before discovering the defective clock distribution chip. Moreover, such a defect search would typically require a complete computer shutdown because most circuit diagnostic programs in use require a system shutdown before they can be run.
The invention as claimed is intended to automatically perform both AC and DC fault testing of clock distribution chips while the computer is operating.
The advantage offered by the present invention is that the clock distribution chips in a computer may now be automatically checked on-line. This on-line fault testing includes checks not only for DC stuck faults, but also for AC timing faults. In one embodiment of the present invention, the clock distribution circuit speed can be tested to within a few hundred pico seconds.